RK8-E Diskless Control Test MAINDEC-08-DHRKA-E-D (Documentation) MAINDEC-08-DHRKA-B-PB (Paper Tape) Test Addr. PC Description ---------------------------------------------------------------------------------------------- 0 0226 Check if disk motor is off. Status 2200 expected. 1 0235 2 0242 3 0250 4 0256 5 0272 6 0305 7 0314 8 0323 9 0334 Check if DCLR clears AC, try all AC combinations 10 0343 0363 11 0365 12 0410 13 0424 13 0441 15 0454 0505 Verify that DLAG loads sector and surface 16 0507 17 0537 Verify that disk address can be loaded and shifted into ldb 18 0561 19 0604 20 0616 21 0633 0645 Verify that DCLR(01) does not clear surface and sector 22 0647 23 0673 24 0720 25 0742 0765 Verify that DCLR(!=10) does not affect CRC using DLAG and DLDC 26 0767 1026 Is CRC not affected by DLDC,DSKP,DRST,DLCA and read buffer? 27 1030 1045 Verify that write lock inhibits load address when set 28 1047 1075 DCLR,DLCA,DRST,DLDC,DSKP and read buffer affect sect & surf? 29 1077 1130 Verify that command register is not affected by DLCR,... 30 1132 1150 Verify that recalibrate inhibits load command on DLDC 31 1152 1171 Verify that recalibrate inhibits load disk address on DLAG 32 1173 33 34 35 36 37 38 39 40 41 1526 42 43 44 45 1615 1650 46 47 48 49 2000 2033 Verify that Data Request Late occurs when ldb is empty 50 2035 2075 51 2077 2115 Verify that DSKP skips on DRL error 52 53 2134 2157 54 2200 2226 55 2253 2230 Verify that recalibrate does set drive status error 56 2270 2255 57 2306 2272 58 59 60 61 62 2444 2466 Does maintenance mode inhibit drive status error skip? 63 2470 2526 Does recalibrate, then DCLR set control busy and status error? 64 2530 2566 Does recalibrate, then DRL set DRL, status error and done? 65 2600 2634 Does recalibrate, then DLCA set control busy and status error? 66 2636 2655 67 2657 2675 68 2677 2716 Verify that skip occurs on control busy error 69 2720 2751 Verify that DCLR(0) clears all of status register 70 2753 2775 Verify that interrupt occurs on control busy error 71 2777 3042 Verify that read buffer,DCLR,DRST,DLAG,DSKP not affect status 72 3044 3116 Does word count overflow after 256 12-bit-shifts and set done? 73 74 3271 3341 Does half block flag in command register work? 75 76 77 3443 3471 Verify data break at loc. 0 of current field with "write" 78 79 80 81 82 83 84 3737 3777 Verify current address increments from 7777 to 0 on "write" 85 4001 4052 Verify current address increments from 200 to TST85 on "write" 86 4054 4153 Is write inhibit set after 256 breaks and cleared by DLAG? 87 4200 4272 Is write inhibit set after 128 breaks and cleared by DLAG? 88 4274 4321 Verify "read" data break at 0000 and 7777 89 90 91 92 93 94 Verify that command 2 causes a "read" data break 95 Verify that command 3 causes a "read" data break 96 - - - 97 5000 5027 Verify that command 6 causes a "read" data break 98 Verify that command 7 causes a "read" data break 99 5063 5127 Verify that all data buffers can be full by "read" data break 100 101 102 103 104 105